Performance Analysis of Wrong-Path Data Cache Accesses

The performance of today's high-end microprocessors continues to grow. This increase in performance is due in part to the use of speculative, out-of-order execution, coupled with highly accurate branch prediction. However, even with branch prediction accuracies over 90%, many instructions are executed unnecessarily from the wrong path. This wrong-path execution results in cache pollution and unnecessary bus traffic. We use an extended version of the SimpleScalar simulation tool to model an out-of-order, 4-way issue processor. First, we use various branch confidence mechanisms to determine if a data access is likely on a mispredicted path or not. Next, we sort the data cache accesses using these confidence mechanisms and compare the “inherent re-usability” of data that is marked either “low confidence” (i.e. likely on the wrong path) to those marked “high confidence” (i.e. likely on the correct path). Finally, with the assistance of small buffers associated with the first level data cache, we try to increase this re-usability factor by preventing low confidencedata accesses from being written into the data cache. We discuss the effectiveness of this technique as well as the behavior and reuse of speculative data.